Description: 收集了很多好的风格及代码的指导准则供参考，遵守这些代码风格及代码指导准则可以提高VHDL程序的可读性，且易于修改。-collected a lot of good style and code guidelines for reference, compliance with these codes and code style guidelines VHDL procedures can improve the readability and easy to change. Platform: |
Size: 39936 |
Author:zcx |
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Description: synopsis的有限状态机编码方法的文档。
针对synopsis的综合环境，根据其综合工具的特点说明安全可靠、速度适合的FSM编码风格。
FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand.-synopsis of the finite state machine coding documents. Synopsis for the integrated environment, in accordance with its characteristics of integrated tools that secure and reliable, speed appropriate FSM coding style. FSM coding style under synopsis. Used for verilog or vhdl designer. Good study data for ASIC newhand. Platform: |
Size: 119808 |
Author:road |
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Description: verilog的非常好的材料，是verilogHDL编码风格的总结。-Verilog s very good material is a summary of verilogHDL coding style. Platform: |
Size: 221184 |
Author:liujakie |
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Description: VHDL代码编写规范与风格，XILINX培训用教材，WORD文档的，写得特好，只不过是E文的-VHDL coding and style norms, XILINX training materials, WORD documents, and written special good, but is E-man Platform: |
Size: 154624 |
Author:邓子龙 |
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Description: 讲述了HDL编码风格的一本好书，不论使用VHDL或verilog的都可以-HDL coding style tells a good book, regardless of the use of VHDL or verilog can take a look at the Platform: |
Size: 211968 |
Author:aegis |
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Description: 一个很好的关于verilog的PPT
第1章 EDA设计与Verilog HDL语言概述
第2章 Verilog HDL基础与开发平台操作指南
第3章 Verilog HDL程序结构
第4章 VERILOG HDL语言基本要素
第5章 面向综合的行为描述语句
第6章 面向验证和仿真的行为描述语句
第7章 系统任务和编译预处理语句
第8章 VERILOG HDL可综合设计的难点解析
第9章 高级逻辑设计思想与代码风格
第10章 可综合状态机开发实例
第11章 常用逻辑的VERILOG HDL实现
第12章 XILINX硬核模块的VERILOG HDL调用
第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design Platform: |
Size: 27825152 |
Author:lyy |
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